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@sswetha18 sswetha18 commented Nov 11, 2025

This commit introduces support for Intel Wildcat Lake (WCL) enabling Zephyr RTOS to run on this platform. New additions include complete board definition and configuration, SoC support for the Wildcat Lake platform, device tree definitions and CPU bindings, GPIO driver extensions, and test overlays for peripheral validation.

@sswetha18 sswetha18 changed the title Wcl board def boards: intel: Add WCL board support Nov 11, 2025
@sswetha18 sswetha18 force-pushed the wcl_board_def branch 2 times, most recently from 5aa79e2 to 5e317b2 Compare November 11, 2025 15:53
@sswetha18 sswetha18 marked this pull request as ready for review November 12, 2025 03:09
@zephyrbot zephyrbot added area: Boards/SoCs area: SPI SPI bus area: Devicetree Bindings area: UART Universal Asynchronous Receiver-Transmitter platform: X86 x86 and x86-64 area: GPIO area: Disk Access area: Tests Issues related to a particular existing or missing test platform: Intel Intel Corporation labels Nov 12, 2025
@sswetha18 sswetha18 force-pushed the wcl_board_def branch 2 times, most recently from 96a6002 to 37c84c5 Compare November 12, 2025 05:46
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PR should be split into multiple commits e.g. one for adding SoC, one for adding board

@sswetha18 sswetha18 force-pushed the wcl_board_def branch 2 times, most recently from f972748 to 64adf5a Compare November 12, 2025 10:48
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It seems some patch ordering issues are still here, otherwise looks good.

Do check now

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@nordicjm @edersondisouza @tejlmand Fixed all the received comments. If no other changes required, Do approved this PR.

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@nordicjm @edersondisouza @tejlmand Fixed all the received comments. If no other changes required, Do approved this PR.

Pro tip: in the top right is this
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click the refresh button next to names so people know your PR is ready to review, without doing that it doesn't appear in review lists and people are unlikely to remember after going through 200+ emails to look the PR up and find it :)

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@nordicjm @edersondisouza @tejlmand Fixed all the received comments. If no other changes required, Do approved this PR.

Pro tip: in the top right is this image click the refresh button next to names so people know your PR is ready to review, without doing that it doesn't appear in review lists and people are unlikely to remember after going through 200+ emails to look the PR up and find it :)

Done

nordicjm
nordicjm previously approved these changes Nov 21, 2025
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It seems some patch ordering issues are still here, otherwise looks good.

Do check now

The ordering issues are still there: including wildcat_lake.dtsi before the file is added, and the hpet binding clock-frequency property being fixed on next patch. Maybe simply squash the "dts" patch into the "boards" one?

This commit introduces SOC support for
Wildcat Lake.

Signed-off-by: S Swetha <s.swetha@intel.com>
Add wildcat lake yaml

Signed-off-by: S Swetha <s.swetha@intel.com>
Fix HPET Clock-frequency property in yaml file

Signed-off-by: S Swetha <s.swetha@intel.com>
This commit introduces device treee source for
Wildcat Lake platform

Signed-off-by: S Swetha <s.swetha@intel.com>
This commit introduces board defintion for Wildcat Lake.

Signed-off-by: S Swetha <s.swetha@intel.com>
This commit introduces overlay files for intel
Wildcat lake boards

Signed-off-by: S Swetha <s.swetha@intel.com>
Swap PAD_CFG1_IOSTERM_PU and PAD_CFG1_IOSTERM_PD values.

Signed-off-by: S Swetha <s.swetha@intel.com>
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It seems some patch ordering issues are still here, otherwise looks good.

Do check now

The ordering issues are still there: including wildcat_lake.dtsi before the file is added, and the hpet binding clock-frequency property being fixed on next patch. Maybe simply squash the "dts" patch into the "boards" one?

Fixed. Do check now

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@edersondisouza Do review

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@edersondisouza Please review the updated changes

@nashif nashif assigned edersondisouza and unassigned nordicjm Nov 24, 2025
@kartben kartben merged commit e891ca6 into zephyrproject-rtos:main Nov 24, 2025
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area: Boards/SoCs area: Devicetree Bindings area: Disk Access area: GPIO area: SPI SPI bus area: Tests Issues related to a particular existing or missing test area: UART Universal Asynchronous Receiver-Transmitter platform: Intel Intel Corporation platform: X86 x86 and x86-64

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8 participants